In SRAMs there have developed various architectures which divide the memory array into sub-arrays in order to save power. In furtherance of this technique, a technique for dividing the memory into sub-arrays by dividing the word lines and bit lines with row and column decoders, respectively, was developed. Such a technique is described in U.S. Pat. No. 4,482,984, Oritani. This was useful for dividing into four sub-arrays. The power loss due to discharging the bit lines was reduced due to reducing the length and thus the capacitance of the bit lines. This had the advantage of saving power.
In advanced SRAMs, however, address transition detection is used to precharge various lines used for sensing data. By precharging less than all of the memory in response to an address transition, power is saved. As density increased, the need to divide the memory into even more sub-arrays resulted in another divided word line technique. In this technique, the memory is divided into sub-arrays in which only one sub-array has an activated word line. A further aspect of this approach is that there is a global row decoder which generates row select signals which traverse more than one sub-array. Each sub-array has its own word line drivers which are coupled to the row select signals. The word line drivers are enabled by a block select signal which is active when that sub-array (or block) with which the block select signal is associated is selected. This approach is described in an article entitled "A 64Kb Full CMOS RAM with Divided Word Line Structure", 1983 IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pgs. 58-59. This approach has the advantage of reducing the word line length, which reduces the delay as well as reducing the current required to charge the word line. The capacitance of the lines which carry the row select lines is less than word lines of comparable length because these row select lines are not connected to the inputs of the memory cells in the memory array. Consequently, the time required to activate a divided-word-line is reduced.
This does not, however, reduce the bit line capacitance because the bit lines are not reduced in length. Consequently, there is no reduction in the time for sensing the data on the bit lines once the word line has been activated.